Design Verification Tech Lead- SerDes/PHY IP

Onsite San Jose, California, United States

python design verification sce

greenhouse

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Job description

You will lead the functional verification of high-speed SerDes/PHY IP in San Jose. This role involves collaborating with cross-functional teams to ensure the success of next-generation AI systems.

Details

San Jose, California, United States, work from office
$160,000 to $200,000 depending on experience
5+ years of design verification experience
Skills: SystemVerilog, UVM, Python

The work

Architect UVM-based verification environments for SerDes/PHY IP
Develop SystemVerilog/UVM testbenches and execute functional verification
Verify PHY behavior against industry specifications like PCIe and Ethernet
Mentor junior DV engineers and collaborate with cross-functional teams