Senior Engineer, PLL Design

Onsite San Jose, California, United States

s.lsi (r&d)

greenhouse

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Job description

You will design and develop high-performance PLL and clocking subsystems for various applications. This role is based in San Jose, California, and requires hands-on experience in PLL design.

Details

San Jose, California, United States, work from office
$138,000—$206,000 USD
5+ years of experience with a Bachelor's, 3+ years with a Master's, or 0 years with a PhD
Skills in PLL design, deep sub-micron CMOS, IC design CAD tools, and Matlab/Simulink

The work

Design PLLs and clock generation circuits for RF and SerDes applications
Perform PLL system-level modeling, noise analysis, and jitter budgeting
Drive design verification including transistor-level simulation and Monte Carlo analysis
Collaborate with teams to deliver PLL IPs meeting performance, power, and area targets